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Low cost BMS

Posted: Mon, 20 Jan 2014, 03:28
by weber
4Springs wrote:1. 12 front modules working just fine.
2. Add 1 rear module (and two long cables) and I get lots of errors.
Can you try:
3. Add two long cables (connected to each other) but with no module between them.

"UTP" stands for "Unshielded Twisted Pair".

If it is just due to cable length, you might try reducing R7 (phototransistor pullup) on the receiving module from 2k2 to 1k8, 1k5 or 1k0. But really, you should borrow that 'scope and see what's happening to the waveform.

[Edit: Added "(connected to each other)"]

Low cost BMS

Posted: Mon, 20 Jan 2014, 10:43
by 7circle
Just reading through posts and learning lots on ways to make low cost BMS.

I got worried this could be taken that conformal coating the Circuit will fix clearence faults.
Weber was discussing mainly creepage ... just trying to clarify :?
weber wrote: ....
I'm also horrified to see a beautiful optocoupler with 7.6 mm creepage and a 600 V continuous rating, with its input unnecessarily surrounded by parts at cell potential in such a way that the creepage is reduced to about 1.3 mm and therefore possibly only good for a 72 volt battery, unless the PCB is conformally coated.

Image
....
In normal operation, the voltage stress occurs at two places: The opto on the first cell that receives comms from the master, and the opto in the master that receives comms from the last cell.
....


Adding a "conformal coating" will help stop pollution and humidity effect creepage rating
But, the coating may not flow/seep under components and leave air gaps.
It can also lift or bubble due to vibration or gas vapour release from heat under the coating.
The area may still be sealed from "pollution" but it will have air as the dielectric to breakdown.

So point to point clearence in air would still need to be considered.

The track to "D_in" pin 1 and the via above are very close, how close is it?
3/1000" ..... Would you want more than 5V across it.(or negative 5V)
(The via looks directly connected to pin 7 of uCro the temp AD input)
Sometimes where the breakdown occurs the circuit components just happen to survive and just cause nuesance faults.
Would Reporting watchdog reset faults or similar after reboot via comm's to BMS master be helpful?
If no CRC checks is there parity checks?

When the BMS interconnects don't follow the series connections of the cells there are more points for Voltage stresses above the single cell voltage.
(Also worrying, I'm sure I've seen BMS linkages with wire rated below 100V. )

Regarding the comm's interfence issue, would adding a load resistance and capacitance in parallel with the opto LED at the opto , stop induced spikes on the BMS interconnect pair wires.
The opto output may have RC filter for baud rate allowance but if LED is triggered by long duration changing large currents win the battery cables inducing MMF to BMS circuit, the RC filter won't help bit errors.

I hope this ramble makes some sense...
7C   Image

Low cost BMS

Posted: Mon, 20 Jan 2014, 11:35
by arber333
4Springs wrote: Can you post a picture of your UTP? My understanding of UTP was "Un-Twisted Pair" - just a single wire.
I don't have any 12V anywhere near the comms at the moment. There is almost nothing powered in the car, probably just the clock!
http://2.bp.blogspot.com/_DZhhZp9of5I/T ... le_ekl.jpg
OK, UTP means "Unshielded Twistet Pair" and it is exactly that. Wiedly used in networks it is very cheap and convenient. It has 4 pairs (8 wires). Be sure to use one with soft wires, because of vibrations. Another version is FTP, "Foil-screened Twisted Pair" Which is used to block EMI out but you have to be certain of your ground points...
4Springs wrote: I am using the same opto that Neville suggested. I saw in your notes though that you were filtering on the Master. Did you ever do it for the modules? I am having the trouble from one module to the next.
Huh, shouldnt be much different. Connect the packs and make one Y cable to put between cells. Check in last box with your scope for comm shape. Check every cell output. If it is distorted then EMI is to blame if you find nice square pulse then either your wire is bad quality or some optos may be bad.
From my experience i used cheap preassembled wires first. Constant problems and what seemeed EMI. When i made my own from UTP cables (the short links) I never had problems. Even if they seem flimsy, those black poloulu connectors hold to their fastons.

I noticed one more thing. As i said BMS was made for bottom balancing. Probably RC values were calculated for 2,5V - 3,6V. Now i noticed if i set charger cutoff point above 3,8V master is reset whenever it tries to handle it. Probably comm output resistors R6 (330R) which i suspect are not enough at 3,8V and opto LED overflows. I will probably changed them this spring on major maintenance. Until then i have the cutoff point to 3,75V and comms seem to be ok.
The only comms reset now is at balancing when cell temp goes to high. This is why i will need your code to help me determine where from...

A

Low cost BMS

Posted: Mon, 20 Jan 2014, 16:08
by woody
arber333 wrote: Well actually i believe i hurt one of my cells.
When i charge at 40A it is the first one to reach 3,55V, but when i lower to 5A it falls down among other cells. Usually at this time i charge at 5A since other cells start to balance. In about 15min i have 42 cells leveled save one. This one - same one that was 3,55V at 40A now climbs slowly from 3,40V to 3,55V. If i disconnect charger it will drift to 3,43V in a matter of hours.
I figure internal resistance must be higher than others. Yet it holds charge as well as others. I guess a year of bottom balancing caused some damage...
It could be a high resistance connection between the terminal and the next cell + BMS - at 40 amps, a resistance of 10 mOhm will give you 0.4 volts higher reading (and put out 16 Watts).

Low cost BMS

Posted: Mon, 20 Jan 2014, 23:52
by arber333
woody wrote:
It could be a high resistance connection between the terminal and the next cell + BMS - at 40 amps, a resistance of 10 mOhm will give you 0.4 volts higher reading (and put out 16 Watts).


Very well, i will try to sand-in my terminals and retorque them. Maybe it will help some, but i doubt it. In addition with this i also see increasing V drop after charge. When other cells hold their voltage for at least a day or so, this one drops cca 0.1V an hour. This is probably not a coincidence, but i drove further than regular and this cell was the first that dropped over the Vlow knee (2,5V) under load.

tnx

A

Low cost BMS

Posted: Tue, 21 Jan 2014, 03:00
by 4Springs
7circle wrote: Just reading through posts and learning lots on ways to make low cost BMS.
Me too - the trouble is I've already built one!
7circle wrote:The track to "D_in" pin 1 and the via above are very close, how close is it?
About 1mm. And about 1.5mm from pin 1 of the opto to R8.
I have a vague plan that I can lift the legs of that opto on any boards that I think might matter the most. Solder comms cable straight to the legs, and pot the whole contraption with a hot glue gun.
7circle wrote:If no CRC checks is there parity checks?
I don't think Neville ever implemented parity checks. He didn't do CRCs because his modules passed everything on character by character. Mine buffer the whole data packet before passing it on, so it was easy for me to do a CRC.
7circle wrote:(Also worrying, I'm sure I've seen BMS linkages with wire rated below 100V. )
I was wondering about this for my cat 5 cable. What is the voltage rating between pairs? I planned the route that the comms takes with the idea that I should reduce voltage differences, but that long run is difficult. The two pairs would normally be about 20V difference, but as Weber said, this could be much higher under certain situations.
7circle wrote:I hope this ramble makes some sense...
Well no actually you lost me on that last bit. Image But I'll go back and have another read on my next EV day!

Low cost BMS

Posted: Tue, 21 Jan 2014, 11:54
by Nevilleh
Pleased to see this topic is still alive and well!
I may have mentioned that I sold my car last year and so haven't been at all involved with EVs since,but I had a PM about my AH meter so I thought I have a look on here as well. Good to see lots of advances and improvements. Keep up the good work!
I note a bit of discussion about clearances around the opto and I want to point out that the voltage between boards is only the cell voltage, so I didn't worry about preserving the high voltage isolation of the opto, except at the master input. Of course, if there was a cell failure that voltage could become equal to the battery voltage, but I didn't think that a very likely scenario and hopefully the bms data would warn one of an impending failure.
I did over 6000 kms in my BMW without any problems and the battery was performing about the same when I sold it as when I first got it going. I did change it to top balancing after a few months and I have to say the range improved noticeably. Getting more energy into the battery I suppose.
The new owner is very happy with it too.
I didn't suffer any significant interference issues just using UTP - hand made, by the way, by winding up two lengths of wire with an electric drill.
I didn't bother with parity checks as I don't believe they offer any significant benefit. Hard to justify CRC checking on a single byte as well! Of course the data packet grows in length with each module, so the CRC becomes more and more justifiable as the number of cells grows and I had thought about adding it in later, but I didn't experience any significant data corruption so never bothered. Remember that the thing polls several times a second, so a bad data packet gets replaced very quickly.
Anyone wants to experiment with adding CRC, I have a very neat and concise implementation (in C) that I used on some other comms stuff and was going to stick into this.

Arber's mods look like they have improved it too!

Low cost BMS

Posted: Tue, 21 Jan 2014, 23:59
by arber333
Hi Neville

Your BMS works in my Mazda dayly now. And now i have 12000km on it. I noticed something when i tried to calibrate charger.
When i added high voltage charger off function in the code and set it for 3,8V, master was reset if one cell went over it. When i fiddled with it i lost my patience and just lowered limit to 3,75V and that supprisingly worked.
I first taught it would be 330R opto resistor on the output from the module. If it would be calculated for 2,5V - 3,6V, but at 3,8V it could saturate opto LED. What do you think if i changed it to 470R?
Problem is i tried single modules in my workshop and they do not exhibit any changes in comm either good or bad. I would have to change resistors on the whole line for effects to be felt... But since i charge to 3,55V per cell it is not a big deal for me. But maybe someone would need to go to 3,8V though.

tnx

A

Low cost BMS

Posted: Wed, 22 Jan 2014, 11:39
by Nevilleh
Can't see any reason why the thing would reset with that value. The voltage can go as high as 3.99v without over- or under- flowing. I don't think I put any range checking in there, but it shouldn't cause a reset no matter what. I wonder if it is a watchdog reset? In which case maybe a s/w bug, but if its a hardware reset you need to check voltages etc.
I seem to vaguely recall that the micro does register watchdog resets somewhere and you may be able to access that. I'll go have a read of the data sheets and let you know if I find anything.
Edit:
I guess you put your own charger control circuitry in it. Can you show what that is please?

Low cost BMS

Posted: Wed, 22 Jan 2014, 20:28
by 4Springs
Right. I'm looking at a scope image of my data but I'm not understanding.

To recap, I have modules communicating with each other via twisted pair UTP at 9600 baud. Each module output drives an optocoupler on the input of the next module. R6 (330R) is the pullup resistor on the output, R7 (2k7) is the pullup on the input.
UTP between adjacent cells is hand-twisted. UTP between front and rear battery boxes is cat-5 cable, looking exactly like the picture that Arber linked to.

The 'scope shows me that every packet is being transmitted from front to rear. The packets at this stage are small, having only visited one module (one byte per module, plus one byte each for command, CRC & terminator).
The packets go around the rear 36 modules without incident - the 'scope shows every packet leaving the last module and heading back towards the front of the vehicle. Packets get larger as they go, and they will be 40 bytes long at this stage. If there were any errors received by a module it would not pass that packet on. So the fact that I see regular packets at this point means that there have been no errors so far.

Image
Phuzy photo of waveform showing data arriving into the front from the back, showing groups of 6 packets being sent from the last module in the back.

When I look at the output from the first module after the data comes back to the front, I see that very few of the packets are re-sent.
Image
This photo shows the data that the next module transmits. So you can see that many of the packets were not transmitted, presumably due to the CRC check failing. My CRC is simple, and some errors still get through, so the Master is occasionally complaining about low cell voltages.

So, I had a close look at the waveform to see if I could find some noise:

Image
This is a picture of a beautiful waveform coming from the unconnected end of the UTP at the receiving end. Note the peak-peak voltage of 3V.

Image
This is what it looks like when connected to the Data In connector (i.e. the optocoupler) of the next module. The voltage is less, but the waveform looks clean to my untrained eye.

Image
This photo is on the other side of the optocoupler. So this is what the microcontroller sees. This is the worst waveform I've seen, there is a bit of a slope on those vertical lines. But that can't be due to the long comms run can it? Sure enough, if I look at another module with only a short wire on the input, the waveform looks the same:
Image

So is there a clue here for my problem? Everything looks fine to me, except that the data is not coming through.
I did try swapping modules around, and the problem stayed with whichever module was connected to that long return line. I also tried swapping the two pairs that I used, so the TX line became the RX line and vice-versa, with no effect. I have previously tried a completely different line, a hand-wound UTP.

Low cost BMS

Posted: Wed, 22 Jan 2014, 20:49
by Richo
Perhaps the signal is ok but it's reference to ground is the problem.
Induced currents may give an overall offset in your signal and trigger bad bits.

Low cost BMS

Posted: Wed, 22 Jan 2014, 21:32
by 4Springs
weber wrote:
4Springs wrote:1. 12 front modules working just fine.
2. Add 1 rear module (and two long cables) and I get lots of errors.
Can you try:
3. Add two long cables (connected to each other) but with no module between them.

I did this, although I wasn't sure why weber was asking me to.
The result of test 3. was that I received no errors. Not one. With rear module = errors, without rear module = no errors. The two long runs (to and from the rear) are in the same cable, so I just unplugged them from the rear modules and plugged them into each other. So the signal went down one and back the other without a module to repeat it.
Then I read this:
Richo wrote: Perhaps the signal is ok but it's reference to ground is the problem.
Induced currents may give an overall offset in your signal and trigger bad bits.
Again, I'm not sure I understand this. If the signal is isolated through the optocoupler, does it have a reference to ground?
If I had an induced current would it show up twice as bad with the above test, or would it cancel out?

Low cost BMS

Posted: Wed, 22 Jan 2014, 21:50
by weber
4Springs wrote:I did try swapping modules around, and the problem stayed with whichever module was connected to that long return line.

Connected to which end of that long return line? Have you tried swapping a new module in for the receiving module at the front as well as the sending module at the back? The clock frequency of one or the other might be off.

Those two photos showing individual bits - could they have been swapped? The one that you say was with the short wire has a longer rise-time (about 0.4 bit time to 90%) than the one you say was with the long wire (about 0.25 bit time to 90%).

As I mentioned earlier, you might try reducing the value of R7 on the receiving module to 1k5. It is shown as 2k2 on the schematic, but you said it is 2k7. This would reduce the abovementioned rise time. The drawback of a lower value pullup on the phototransistor is that it may not pull all the way down when the transmitting module's cell voltage is very low. But I calculate that 1k5 should work down to 2.0 V which is what the PIC is rated down to.

But the rise-time is not so bad that it is likely to be the cause. And your results for test 3 suggest that it is the rear module that is at fault.

Low cost BMS

Posted: Wed, 22 Jan 2014, 22:16
by 4Springs
My answer to:
weber wrote: Have you tried swapping a new module in for the receiving module at the front as well as the sending module at the back?
was "yes". But I decided to go and do it again just to make sure.
Result is that I found it was indeed a problem with one of the rear modules. I am now bypassing this one (i.e. sending from the one before), and it is working without errors.
I was sure that I had done this test before (bypassed that module), but that is why we do double-checking. Thanks weber!

Low cost BMS

Posted: Wed, 22 Jan 2014, 22:18
by weber
4Springs wrote:
7circle wrote:The track to "D_in" pin 1 and the via above are very close, how close is it?
About 1mm.
No. It's a lot closer than that. 7Circle is considering the creepage under the solder-mask from the track to the via. It looks like only 0.2 mm to 0.25 mm to me. That's only good for 30 volts according to this: http://www.smps.us/pcbtracespacing.html. Or 125 volts if you use the creepage calculator here and at treat it as a coated board requiring basic insulation: http://www.creepage.com/.

According to Wikipedia, the Cat 5 standard only requires that the cable be rated to 57 V, although some manufacturers rate it to 125 V.

Low cost BMS

Posted: Wed, 22 Jan 2014, 22:32
by 4Springs
weber wrote:
4Springs wrote:
7circle wrote:The track to "D_in" pin 1 and the via above are very close, how close is it?
About 1mm.
No. It's a lot closer than that. 7Circle is considering the creepage under the solder-mask from the track to the via. It looks like only 0.2 mm to 0.25 mm to me.
I put a board up to the light and took a photo:
Image

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Posted: Wed, 22 Jan 2014, 22:55
by weber
4Springs wrote:I put a board up to the light and took a photo:
You win! I was apparently looking at old artwork:

Image

I'm glad to see that was improved before it went to fabrication.

Low cost BMS

Posted: Thu, 23 Jan 2014, 12:05
by Nevilleh
Your waveforms look pretty good. RS232 is very tolerant and doesn't care too much about rise and fall times and even the clock rate can be nearly 10% out without causing many errors. Remember that a "byte" is 10 bits long and it syncs off the first edge of the start bit, waits 1/2 bit period and then samples at bit periods after that until it has 8 bits and finds the stop bit at the appropriate time and the correct level. This means that even if the edges are quite "droopy" as long as the level is correct at the sampling point, it'll work OK. The key things are a reasonable edge to the start bit and a clock that stays within 1/2 a bit period over the full 10 bits.
Reading the other messages, it became pretty obvious that you had a faulty module.

Low cost BMS

Posted: Thu, 23 Jan 2014, 16:19
by weber
Nevilleh wrote: Your waveforms look pretty good. RS232 is very tolerant and doesn't care too much about rise and fall times and even the clock rate can be nearly 10% out without causing many errors. ... The key things are a reasonable edge to the start bit and a clock that stays within 1/2 a bit period over the full 10 bits.

1/2 a bit period over 10 bits is 5%, not 10%. And _equal_ rise and fall times don't matter much; in fact it can look like a sine wave. But any _asymmetry_ in the rise and fall times eats into that 5%. e.g. if the signal at the micro input has an essentialy zero fall time but it takes 0.15 of a bit time to _rise_ to the schmidt threshold (as it does in the last of 4Springs' photos above) then the error can only be 0.5 - 0.15 = 0.35 bit periods in 10, or 3.5%. But that's the allowable _difference_ between transmit and receive clocks. So the transmit and receive clocks would only need errors of 1.75% in opposite directions for comms to fail. And that assumes clock jitter is negligible.

4Springs, I wouldn't be so quick to blame the rear transmitting module. As per the above, success on bypassing it _could_ be because the modules before and after it have clock frequencies that are off in the same direction. Or the blame could be shared between them and the bypasssed module. It takes two to tango. Do you have a way of measuring a module's clock frequency?

[Edit:] Coulomb and I trim ours to within 0.5%. We have a command in our TestICal (test, ID and calibrate) software that puts out a frequency-divided clock on an output that we measure with a meter. Then we nudge the DCO calibration value up or down as required.

Low cost BMS

Posted: Thu, 23 Jan 2014, 16:39
by Nevilleh
Plus or minus 5% makes a 10% spread. And the rise and fall times don't eat into it much - as long as the voltage is past the threshold, the input (Schmitt, probably) will see it as a 0 or 1. The RS232 spec says something like 3-15 volts , + and - but I've found it works very well using logic levels, 0 and +5 v which is what the bms uses. I've never bothered to try and measure the actual voltage level where a "mark' becomes a "space" but it certainly sees 0V perfectly happily ie it doesn't need a negative voltage.
So I doubt very much that 4 Springs errors are caused by clock variations. More likely a dud opto or something like that.

Low cost BMS

Posted: Thu, 23 Jan 2014, 17:05
by 4Springs
weber wrote:
4Springs, I wouldn't be so quick to blame the rear transmitting module. As per the above, success on bypassing it _could_ be because the modules before and after it have clock frequencies that are off in the same direction. Or the blame could be shared between them and the bypasssed module. It takes two to tango. Do you have a way of measuring a module's clock frequency?

Only easy way I could think of was to measure the waveform coming out of a module.
I measured 21 bits using the CRO. At 9600 baud, this should take 2187 uS. I estimate my resolution as 20uS (I'm reading from a display on an old DSO that doesn't allow me to pan or zoom).
Board that gave me grief: 2320 uS
Board I replaced it with: 2320 uS
Board that does the receiving (in the front): 2320 uS

So I'm pretty happy that the timing is consistent between these three. It is not quite exactly 9600 baud, but that is probably the maths in the modules.
I need to take that problematic board off and give it a good going over. I may have a dry joint somewhere.


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Posted: Thu, 23 Jan 2014, 19:44
by weber
Hi Nevilleh.

Although it is clear now, thanks to 4Springs' measurements, that it is not a clock speed problem, you seem to have failed to understand both of the points I made in my previous message.
Nevilleh wrote: Plus or minus 5% makes a 10% spread.

But you don't get to _have_ plus or minus 5%. You only get to have +-2.5%. If a module with a plus 3% clock is talking to one with a minus 3% clock there will be a 6% difference between them and comms will fail. So you don't get to have a 10% spread, only a 5% spread. And that's ignoring all the other things that eat into this margin.
And the rise and fall times don't eat into it much
They don't eat into it at all. What eats into it is the _difference_ between rise and fall times.
- as long as the voltage is past the threshold, the input (Schmitt, probably) will see it as a 0 or 1.
Of course. (Schmitt, definitely). The issue is _when_ it will see the flip from a 0 to a 1 at the beginning of the stop bit (or last data bit), relative to when it saw the flip from a 1 to a 0 at the beginning of the start bit.

Looking at it another way: If rise time is longer than fall time, 1 bits get narrower and 0 bits get wider from the processor's point of view, so 1 bits become a smaller target to hit when sampling, so you have less margin for frequency error.

A 1 bit whose rising edge is delayed by slow rise time (relative to start-bit fall time) looks exactly the same as a bit whose rising edge is delayed by a slow transmit clock. So the two effects add.
The RS232 spec says something like 3-15 volts , + and - but I've found it works very well using logic levels, 0 and +5 v which is what the bms uses. I've never bothered to try and measure the actual voltage level where a "mark' becomes a "space" but it certainly sees 0V perfectly happily ie it doesn't need a negative voltage.
I don't understand why you are talking about RS232 voltage levels or negative voltages. I certainly wasn't assuming anything that relates   to them. All that matters re 4Springs problem is what levels the modules use to communicate with each other, and that isn't 0 and +5 V either. It's nominally 0 and +3.3 V at the micros and something like 0 and 5 mA on the cable.

You don't _measure_ where a mark becomes a space. You look up the worst case in the datasheet.
http://ww1.microchip.com/downloads/jp/D ... 547368.pdf
Schmitt thresholds are at 0.2 and 0.8 times Vdd (worst case).

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Posted: Thu, 23 Jan 2014, 20:13
by Nevilleh

What is it they say about teachers?

Low cost BMS

Posted: Thu, 23 Jan 2014, 20:40
by weber
Nevilleh wrote:
What is it they say about teachers?

What is it they say about gross generalisations and resorting to personal insults?

Edit:

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Posted: Thu, 23 Jan 2014, 20:48
by Nevilleh
weber wrote: Hi Nevilleh.

Although it is clear now, thanks to 4Springs' measurements, that it is not a clock speed problem, you seem to have failed to understand both of the points I made in my previous message.


Is that an insult? Maybe I'm too sensitive. But I didn't fail to understand, I just didn't bother reading it.

I've only worked with serial comms for about 30 years, so maybe I'm a slow learner, but I've always made my stuff work. I can't really be bothered showing the workings for the timings, but I don't agree with your numbers.

And 4Springs problem is not clock related. I rest my case.